1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device which is improved to increase an isolation breakdown voltage of an N-channel transistor. The present invention also relates to a method of manufacturing such semiconductor device. This invention further relates to a semiconductor device including an N-channel field transistor having an improved breakdown voltage.
2. Description of the Prior Art
Among semiconductor memory devices, a DRAM which allows random input/output of memory information is known. Generally, a DRAM includes a memory cell array which is a memory region storing a large amount of memory information and a peripheral circuitry which is required for external input/output.
FIG. 40 is a block diagram showing a structure of a general DRAM. In FIG. 40, a DRAM 50 includes a memory cell array 51 storing data signals of the memory information. A row and column address buffer 52 is provided only for receiving an external address signal for selecting a memory cell constituting a unit memory circuit. An input protection circuit 59 is connected to row and column address buffer 52, and an address signal is passed to row and column address buffer 52 through input protection circuit 59. A row decoder 53 and a column decoder 54 designate a memory cell by decoding the address signal. A sense refresh amplifier 55 amplifies and reads a signal stored in the designated memory cell. A data in buffer 56 and a data out buffer 57 are provided for data input/output. A clock generator 58 is provided for generating clock signals.
The present invention relates to an N-channel transistor in a memory cell array and a high breakdown voltage transistor input protection circuit 59.
FIGS. 41-51 are cross sectional views of a semiconductor device in respective steps of a manufacturing process of a conventional CMOS field effect transistor.
Referring to FIG. 41, a field oxide film 2 is formed for isolation through the LOCOS method at a main surface of a silicon substrate 1.
Referring to FIG. 42, a P-channel transistor region 3 is covered with a resist 4, and boron 6 is implanted into an N-channel transistor region 5 for forming a well under conditions of implantation energy: 1 Mev and implantation concentration: 1.times.10.sup.13 atoms/cm.sup.2. Boron 7 is implanted for a channel cut of field oxide film 2 under conditions of implantation energy: 150 KeV and implantation concentration: 5.times.10.sup.12 atoms/cm.sup.2. Then, boron 8 doped for a channel is implanted for determining V.sub.th of the N-channel transistor under conditions of implantation energy: 50 KeV and implantation concentration: 3.times.10.sup.12 atoms/cm.sup.2.
Referring to FIG. 43, N-channel transistor region 5 is covered with a resist 9, and phosphorus 10 is implanted into P-channel transistor region 3 for forming a well under conditions of implantation energy: 1.2 MeV and implantation concentration: 1.times.10.sup.13 atoms/cm.sup.2. Boron 11 doped for a channel is implanted for determining V.sub.th of the P-channel transistor under conditions of implantation energy: 20 KeV and implantation concentration: 1.times.10.sup.12 atoms/cm.sup.2.
Referring to FIG. 44, a silicon oxide film 12 having a film thickness of about 150.ANG., a phosphorus-doped polycrystalline silicon film 13, and a tungsten silicide film 14 are formed in turn, and thus a gate electrode 15 of a MOS transistor is formed. A portion where boron 7 is implanted will be called a channel cut layer 7a (concentration: 1.times.10.sup.16 -5.times.10.sup.16 atoms/cm.sup.3) hereinafter.
Referring to FIG. 45, P-channel transistor region 3 is covered with a resist 16, and phosphorus 18 is implanted rotationally at an inclination of 45.degree. into a source/drain region 17 of the N-channel transistor under conditions of implantation energy: 50 KeV and implantation concentration: 2.times.10.sup.13 atoms/cm.sup.2.
Referring to FIG. 46, N-channel transistor region 5 is covered with a resist 19, and boron difluoride 21 is implanted into source/drain regions 20 of the P-channel transistor under conditions of implantation energy: 20 KeV and implantation concentration: 1.times.10.sup.13 atoms/cm.sup.2.
Referring to FIG. 47, a sidewall spacer 22 is formed by the silicon oxide film on a sidewall of gate electrode 15. Then, P-channel transistor region 3 is covered with a resist 23, and arsenic 24 is implanted into source/drain regions 17 of the N-channel transistor under conditions of implantation energy: 50 KeV and implantation concentration: 5.times.10.sup.15 atoms/cm.sup.2.
Referring to FIG. 48, N-channel transistor region 5 is covered with a resist 25, and boron difluoride 26 is implanted into source/drain regions 20 of the P-channel transistor under conditions of implantation energy: 20 KeV and implantation concentration: 5.times.10.sup.15 atoms/cm.sup.2. Then, drive treatment (i.e., heat treatment) was conducted for about twenty minutes under O.sub.2 atmosphere at 850.degree. C.
Referring to FIG. 49(a), portions other than the ROM implantation portion (shown in FIG. 49(b)) is covered with a resist 27.
Referring to FIG. 50(a), boron 28 is implanted for ROM determination (with an acceleration voltage of 300 KeV). Thus, ions for writing data (i.e., programming) are implanted into the ROM implantation portion (shown in FIG. 50(b)).
The description of the ROM implantation will be given for reference. ROM is a memory allowing accesses to certain addresses at an arbitrary order, and reading is the main or only operation carried out therein. The above-described ion-implantation program is known as a method for writing data (programming). Referring to FIG. 50(b), by implanting channel ions (28) using ion-implantation mask (27), a threshold voltage of a memory cell transistor 100 is changed such that the data is programmed.
Resist 27 is removed after ROM implantation.
Referring to FIG. 51, an interlayer insulating film 29 is formed on silicon substrate 1 for covering the gate electrode. A contact hole is formed in interlayer insulating film 29 for exposing a surface of the source/drain region, and an electrode 30 is connected to the source/drain region through this contact hole.
Since the conventional semiconductor device has been manufactured by the above-described method, the following problems exist.
FIG. 52 is a profile of a boron concentration in the silicon substrate (i.e., a relationship between depth of the substrate and concentration of boron) taken along line A--A in FIG. 44.
Referring to FIGS. 42, 44, and 52, in the conventional method, boron 7 is implanted deeply with a high energy for a channel cut of the N-channel transistor, and then thermally diffused for forming channel cut layer 7a. At this time, since boron is diffused down under an end 2a of silicon oxide film 2, the concentration of boron is lowered directly under end 2a of silicon substrate 2 (approximately 1.times.10.sup.16 -5.times.10.sup.16 atoms/cm.sup.3 at portion "a" in FIG. 52), and thus the isolation breakdown voltage is decreased.
Also, in the conventional method, the breakdown voltage of the N-channel field transistor (i.e., a high breakdown voltage transistor), which is formed simultaneously with the N-channel transistor, is decreased.
The high breakdown voltage transistor serves to form input protection circuit 59, referring to FIG. 40.
The input protection circuit is provided between a pad and an address buffer, referring to FIG. 53. Input protection circuit 59 includes the N-channel field transistor and the P-channel field transistor, and serves to release noise of input signals externally.
FIG. 54 is a cross sectional view of the N-channel field transistor formed in the input protection circuit. Although the N-channel field transistor 115 shown in FIG. 54 is formed spaced apart from the transistor shown in FIG. 51, they are still formed within the same chip. In FIGS. 51 and 54, portions shown by the same hatching are formed simultaneously.
Referring to FIG. 54, gate electrode 15 consisting of polycrystalline silicon film 13 and tungsten silicide film 14 is formed on field oxide film 2. Field oxide film 2 under gate electrode 15 is thick, and a transistor thus formed is also called a high breakdown voltage transistor.
In FIG. 54, a profile of boron in silicon substrate 1 cut along line A--A is the same as that shown in FIG. 52. The concentration of boron is lowered directly under end 2a of silicon oxide film 2, and accordingly the breakdown voltage of the N-channel field transistor 115 is decreased. Then, a leak current flows to the direction shown by an arrow B, so that it cannot perform its function as an input protection circuit.